Dynamic configuration of input/output controller access lanes

ABSTRACT

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

FIELD

The present disclosure relates to Input/Output (I/O) Controller Access,and more particularly, to dynamic configuration and enforcement ofaccess lanes to I/O controllers.

BACKGROUND

Processor chipsets, or Systems-on-a-Chip (SoCs), are being designed toinclude increasing numbers of relatively high speed I/O controllers(HSIOs), such as, for example, Peripheral Component Interconnect Express(PCIe) controllers, Universal Serial Bus (USB) controllers, Ethernetcontrollers and Serial Advanced Technology Attachment (SATA)controllers. The SoCs may also support lower speed or general purposeI/O controllers, power delivery pins, memory controllers, etc. Thesecontrollers interface to the external world through pins. As a result,an increasing number of pins (a limited resource) of the SoC are beingconsumed.

One solution to this problem has been to multiplex the HSIO controllersto groups of pins (also referred to as HSIO lanes). The controller tolane selection can be accomplished in a static manner, through the useof fuses or pin straps, to create a particular configuration for eachSoC product part number or SKU (stock keeping unit). Because differentcustomers, with different application needs and budgets, may eachrequire different numbers and combinations of each type of HSIO, thenumber of product variations offered for sale (each with its own SKU)may grow rapidly and become more difficult to manage.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of embodiments of the claimed subject matterwill become apparent as the following Detailed Description proceeds, andupon reference to the Drawings, wherein like numerals depict like parts,and in which:

FIG. 1 illustrates a system level block diagram of an example embodimentconsistent with the present disclosure;

FIG. 2 illustrates a more detailed block diagram of another exampleembodiment consistent with the present disclosure;

FIGS. 3(a) and 3(b) illustrate a flowchart of operations of one exampleembodiment consistent with the present disclosure;

FIG. 4 illustrates a flowchart of operations of another exampleembodiment consistent with the present disclosure; and

FIG. 5 illustrates a system diagram of a platform of another exampleembodiment consistent with the present disclosure.

Although the following Detailed Description will proceed with referencebeing made to illustrative embodiments, many alternatives,modifications, and variations thereof will be apparent to those skilledin the art.

DETAILED DESCRIPTION

Generally, this disclosure provides systems, devices, methods andcomputer readable media for dynamic configuration and enforcement ofmappings of I/O controllers to access lanes, for example in aSystem-on-a-Chip (SoC) or server platform controller hub (PCH).Embodiments of the present disclosure may thus reduce SoC pin count andsimplify part provisioning (e.g., SKU numbering and inventory control).The I/O controllers may generally be relatively high speed I/Ocontrollers such as, for example, PCIe, USB, Ethernet and SATAcontrollers, etc., collectively referred to herein as HSIO controllers.The system may be configured to allow a remote agent to: map/re-maplanes to HSIOs; selectively enable or disable any lane; and limit thenumber of available lanes to any desired maximum value. Theseconfigurable properties, which may be collectively referred to as HSIOconfiguration or lane configuration, may all be associated with aparticular SoC SKU. The remote agent may, for example, include softwareexecuting on an OEM (Original Equipment Manufacturer) or ODM (OriginalDesign Manufacturer) provided processor that may be configured asinternal or external to the SoC and that is coupled to the system duringa configuration phase, thus allowing the OEM to configure an SoC as aproduct that meets the particular application requirements of acustomer, end user or data center.

Although embodiments of the present disclosure may be described hereinwith respect to certain types of HSIO controllers (e.g., PCIe, etc.) andparticular SoC components, it will be appreciated that, in general,these principles may be applied to any type of SoC and HSIO controllerand that the term “high speed” is a relative term. For example, 100million transfers/second may be considered high speed for one type ofSoC, while 1 billion transfers/second may be considered high speed foranother type of SoC.

FIG. 1 illustrates a system level block diagram 100 of an exampleembodiment consistent with the present disclosure. The SoC 102 is shownto include a lane mapping module 130 that is configured to map ormultiplex a number (N) of HSIO controllers 120, 122 . . . 124, to accesslanes 140, 142 . . . 144, as will be described in greater detail below.There may be M lanes, where M is typically less than N. In someembodiments, the SoC 102 may also include a power management controller(PMC) 104, a management engine microcontroller (ME) 106, and aninnovation engine microcontroller (IE) and/or baseboard managementcontroller (BMC) 108 that may be configured to dynamically control theHSIO/lane configurations, although, in general, any suitable processorsor controllers may be used for this purpose.

The ME 106 may, in general, be an SoC specific processor that isprovided to configure the SoC during an initial power-up and to provideadditional capabilities including, for example, power and/or thermalmanagement functions. In some embodiments, the ME 106 may haverelatively broad/unrestricted access to most or all internal componentsand functions of the SoC in order to perform these tasks. Additionally,in some embodiments, access to or modification of the ME 106 (forexample through firmware changes) may be limited to the SoCmanufacturer/supplier.

The IE/BMC 108 may, in general, be configured to provide capabilitiesthat are similar to the ME 106, but with increased restrictionsregarding access to internal components and functions of the SoC. Insome embodiments, the BMC 108 may be supplied or controlled by anOEM/ODM, as a value-added platform component to provide additionalcapabilities while in other embodiments the IE could be embedded in theSoC. These capabilities may include, for example, monitoring that theSoC is able to communicate with a system administrator through anindependent connection, and/or providing a generic abstraction of theSoC capabilities that may be shared across different product lines.

SoC 102 may further include flash memory 110 (or other suitablenon-volatile memory) to store default configuration parameters and RAMmemory 112 (or other suitable volatile memory) to store overrideconfiguration parameters. The flash memory 110 may also be configured tostore updated configuration parameters after verification, as will beexplained below. SoC 102 may further include one or more general purposeprocessing cores 114, configured to execute software or applications asrequired by a user of the system and to perform any other suitabletasks.

A hardware (HW) SKU value that is associated with the SoC 102 may beencoded in the SoC by any suitable means that allows read only(non-modifiable) access by the various processors, controllers and/ormicrocontrollers. The SoC 102 may be part of a circuit board or platformas described below in connection with FIG. 5.

FIG. 2 illustrates a more detailed block diagram 200 of an embodiment ofthe lane mapping module 130 consistent with the present disclosure. Lanemapping module 130 is shown to include a plurality of fuses 206 alongwith fuse controller module 202, and a plurality of softstraps 208 alongwith softstrap controller module 204. Fuses may be configured to provideelectrical shorts or opens between HSIO controller signal lines and oneor more of the output lanes. The fuses 206 and softstraps 208 may becontrolled by fuse controller module 202 and softstrap controller module204 respectively, based on information stored in RAM 112 to providedynamic reconfiguration of the connections (e.g., shorts versus opens).The information may be stored in a region of the RAM 112 that isassociated with or accessible to the PMC 104. Lane mapping module 130 isshown to also include a lane multiplexing module 210 configured toprovide a plurality of potential paths between the HSIO controllersignal lines and the output lanes. Lane mapping module 130 is shown tofurther include an active lane selection (or enablement) module 220configured to enable and/or disable one or more selected lanes, forexample based on the SKU. Lane mapping module 130 is shown to furtherinclude a maximum lane enforcement module 230 configured to limit thenumber of active lanes to a maximum threshold value, for example basedon the SKU. The maximum lane count may be referred to herein as “lanewidth.” In some embodiments, any or all of modules 202, 204, 220, 230may be incorporated in ME 106.

FIGS. 3(a) and 3(b) illustrate a flowchart of operations 300 of oneexample embodiment consistent with the present disclosure. An ME 106processor based mechanism is shown as an example for configuration andenforcement of mappings of HSIO lanes. In the following description, thesystem may progress through different power states or levels, forexample from a relatively lower power state (e.g., an off state or sleepstate) to a relatively higher power state (e.g., an operational state).In some embodiments, the power states may comply with states that aredefined in the Advanced Configuration and Power Interface (ACPI)specification, including revision 5.1, published Aug. 12, 2104. Morespecifically, power state G3 may represent a mechanical power off state.Power state S5 may represent a soft power off state, for example wherepower is supplied to the system but a full reboot is required to bringthe system up. Power state S0 may represent a powered up or generallyoperational state, which may be triggered by a wake-up event including akeyboard or mouse event, a clock event or any other suitable type ofinput.

The process may begin with the system in a G3 state 302. Once power isapplied, the system transitions to the S5 state 310. During thistransition, the flash memory controller, at operation 304, reads defaultHSIO lane assignments from flash memory 110 (and/or the fuse controllermodule 202 reads default fuse settings) to be made available to the ME106. The default HSIO lane assignments may also be configured insoftstrap settings. Also, during this transition, at operation 306, thePMC 104 triggers the ME 106 to load HSIO lane reassignments(configuration changes), if any are available, from flash memory 110 toa region of RAM 112 that is associated with or accessible to the PMC104. At operation 308, the HSIO controllers (and any associated analoglogic controllers) read the, potentially modified, softstrap and fuseinformation from RAM 112, thus enabling the ME 106 to apply overrides ofstatic fuse and softstrap settings for HSIO-to-lane mappings and forlane enablement selections.

A wake-up event may then cause the system to transition from the S5state 310 to an S0 state 312, causing one of the processor cores 114 tofetch a reset vector and, at operation 320, to begin executing thesystem BIOS (Basic I/O System). Although the term BIOS is used in thisdisclosure, it will be understood that this term may encompass any typeof firmware including, for example, Unified Extensible Firmware or othervariations of boot loaders, etc. At operation 322, the BIOS checks todetermine if an HSIO configuration change request has been made. Such arequest may be generated by remote software or a remote agent (forexample 560), the IE or BMC processor 108 or by the BIOS itself. Thechange request may occur at any time during the operation or start-up ofthe system. The BIOS may communicate information/status regarding anyconfiguration changes to the ME 106. In some embodiments, communicationbetween BIOS and ME may be through a Host Environment Control Interface(HECI). It will be appreciated that configuration changes provided bythe IE may generally be more secure than changes provided by the BIOS,because, for example, the IE firmware (FW) may be signed and verified bythe IE hardware prior to execution. This is in contrast to the BIOSwhich can be re-programmed and thus the safety of thesignature/verification process can potentially be overridden due togeneric design. In some embodiments, however, it is possible for theBIOS to provide the same level of security if it is signed and verifiedby IE Hardware prior to execution.

If no change is detected, then at operation 324, the ME 106 verifies,for example though execution of firmware, that the current laneconfiguration (including lane mapping, lane enablement selection andlane width) is valid for this HW SKU. For example, the requested numberof HSIO lanes may not exceed the maximum number of lanes (or lane width)allowed for this SKU. Additionally, the lane assignments should becompatible with HW fusing and other HW capabilities. The firmware mayinclude (or consult) a database that provides a listing of validconfigurations for a given SKU. The ME may confirm the validity (orinvalidity) of the configuration to the BIOS, for example through theHECI or other suitable communication path.

If the configuration is valid, then the BIOS may continue with platforminitialization at operation 326. If invalid, then the BIOS may generatea system error, at operation 332, and may continue with platforminitialization or take any other appropriate action. In someembodiments, the system error may be signaled to the remote agent 560 sothat corrective action may be taken.

If the BIOS detects an HSIO change request, then at operation 328, theBIOS forwards the change request to the ME 106. The ME 106 verifies, atoperation 330, that the requested configuration change (including lanemapping, lane enablement selection and lane width) is valid for this HWSKU. The ME may confirm the validity (or invalidity) of theconfiguration to the BIOS, for example through the HECI or othersuitable communication path. If invalid, then the BIOS may generate asystem error, at operation 332, and may continue with platforminitialization or take any other appropriate action. If valid, however,at operation 334, the ME writes the HSIO changes to flash memory 110 andcauses the BIOS to generate a cold reset, at operation 336. The resetreturns the system to the G3 state 302. The reset may or may not includea power cycle of the system.

In some embodiments, the I/O controllers may also include memoryexpansion and/or coherency controllers. It will be appreciated thatembodiments of the present disclosure may enable multiplexing lanesbetween IO controllers and other types of controllers operating ondifferent physical link layer and data link layer protocols.

FIG. 4 illustrates a flowchart of operations 400 of another exampleembodiment consistent with the present disclosure. The operationsprovide a method for configuration of Input/Output (I/O) controller laneaccess of a system. At operation 410, a change request is detected, forexample by the ME. The change request is to modify the configurationfrom an existing configuration to a new configuration. The changerequest may occur at any time during the operation or start-up of thesystem (e.g., SoC). The configuration may include an I/O controller tolane mapping, a lane enablement selection or a lane width. At operation420, the new configuration is verified to be valid based on a stockkeeping unit (SKU) associated with the system. At operation 430, if theverification is successful, the new configuration is stored innon-volatile memory and the system is reset, which may or may notinclude a power cycle. After reset, the new configuration maybe used bythe I/O controllers.

FIG. 5 illustrates a system diagram 500 of one example embodimentconsistent with the present disclosure. A platform 510 may be a systemcircuit board, computing device, workstation or desktop computer, smartphone, smart tablet, personal digital assistant (PDA), mobile Internetdevice (MID), convertible tablet, notebook, laptop computer, or anyother suitable device.

The platform 510 is shown to include an SoC 102, to provide dynamicconfiguration and enforcement of HSIO access lanes, as describedpreviously. Platform 510 may also include any number of other processors520, memory 530, storage systems 540 and any other suitable systemcomponents 550. In some embodiments, the processors 520 may beimplemented as any number of processor cores. The processor (orprocessor cores) may be any type of processor, such as, for example, amicroprocessor, a microcontroller, an embedded processor, a digitalsignal processor (DSP), a graphics processor (GPU), a network processor,a field programmable gate array or other device configured to executecode. The processors may be multithreaded cores in that they may includemore than one hardware thread context (or “logical processor”) per core.

The memory 530 may be coupled to the processors. The memory 530 may beany of a wide variety of memories (including various layers of memoryhierarchy and/or memory caches) as are known or otherwise available tothose of skill in the art. It will be appreciated that the processorsand memory may be configured to store, host and/or execute one or moreuser applications or other software modules. These applications mayinclude, but not be limited to, for example, any type of computation,communication, data management, data storage and/or user interface task.In some embodiments, these applications may employ or interact with anyother components of the platform 510. Platform 510 is also shown toinclude a storage system 540, for example an HDD or SSD.

It will be appreciated that in some embodiments, the various componentsof the platform 510 may be combined in a system-on-a-chip (SoC)architecture. In some embodiments, the components may be hardwarecomponents, firmware components, software components or any suitablecombination of hardware, firmware or software.

An OEM (or vendor) programming/configuration tool 560 is shown coupledto the platform 510 and, in particular, to the SoC 102. The tool 560 maybe any type of processor or computing platform configured to executesoftware to generate HSIO configuration change requests and tocommunicate those requests to platform 560. The configuration changerequest may be generated at any time during the operation or start-up ofSoC. The tool 560 may also be configured to generate and/or downloadfirmware that is executed by the ME 106, enabling further control of theconfiguration process by the OEM. In some embodiments, the firmware maybe written in the Quark programming language.

Embodiments of the methods described herein may be implemented in asystem that includes one or more storage mediums having stored thereon,individually or in combination, instructions that when executed by oneor more processors perform the methods. Here, the processor may include,for example, a system CPU (e.g., core processor) and/or programmablecircuitry. Thus, it is intended that operations according to the methodsdescribed herein may be distributed across a plurality of physicaldevices, such as, for example, processing structures at severaldifferent physical locations. Also, it is intended that the methodoperations may be performed individually or in a subcombination, aswould be understood by one skilled in the art. Thus, not all of theoperations of each of the flow charts need to be performed, and thepresent disclosure expressly intends that all subcombinations of suchoperations are enabled as would be understood by one of ordinary skillin the art.

The storage medium may include any type of tangible medium, for example,any type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritables (CD-RWs), digitalversatile disks (DVDs) and magneto-optical disks, semiconductor devicessuch as read-only memories (ROMs), random access memories (RAMs) such asdynamic and static RAMs, erasable programmable read-only memories(EPROMs), electrically erasable programmable read-only memories(EEPROMs), flash memories, magnetic or optical cards, or any type ofmedia suitable for storing electronic instructions.

“Circuitry,” as used in any embodiment herein, may include, for example,singly or in any combination, hardwired circuitry, programmablecircuitry, state machine circuitry, and/or firmware that storesinstructions executed by programmable circuitry. An application (or“App”) may be embodied as code or instructions which may be executed onprogrammable circuitry such as a host processor or other programmablecircuitry. A module, as used in any embodiment herein, may be embodiedas circuitry. The circuitry may be embodied as an integrated circuit,such as an integrated circuit chip. In some embodiments, a module maythus be implemented in software and/or firmware and may comprise one ormore processes, threads or subroutines of a single process.Additionally, in some embodiments, a module may be distributed andexecuted on separate devices.

Thus, the present disclosure provides systems, devices, methods andcomputer readable media for dynamic configuration and enforcement ofaccess lanes to HSIO controllers. The following examples pertain tofurther embodiments.

According to Example 1 there is provided a system. The system mayinclude a plurality of Input/Output (I/O) controllers; a plurality oflanes; a lane mapping module to multiplex at least one of the I/Ocontrollers to at least one of the lanes based on a configuration; afirst processor to detect a change request, the change request to modifythe configuration from an existing configuration to a new configuration;and a second processor to: verify that the new configuration is validbased on a stock keeping unit (SKU) associated with the SoC; and, if theverification is successful, store the new configuration in non-volatilememory and reset the SoC.

Example 2 may include the subject matter of Example 1, and theconfiguration includes an I/O controller to lane mapping, a laneenablement selection or a lane width.

Example 3 may include the subject matter of Examples 1 and 2, and theI/O controllers load the new configuration from the non-volatile memory,after the reset.

Example 4 may include the subject matter of Examples 1-3, and theverification of the new configuration further includes verifying an I/Ocontroller to lane mapping, verifying a lane enablement selection andverifying a lane width.

Example 5 may include the subject matter of Examples 1-4, and the changerequest detection is performed during a power state transition of theSoC from a lower power state to a higher power state.

Example 6 may include the subject matter of Examples 1-5, and the changerequest is received from an agent external to the SoC.

Example 7 may include the subject matter of Examples 1-6, and the firstprocessor is to execute a Basic Input Output System (BIOS).

Example 8 may include the subject matter of Examples 1-7, and the secondprocessor is a management engine microcontroller.

Example 9 may include the subject matter of Examples 1-8, and theplurality of Input/Output (I/O) controllers include a PeripheralComponent Interconnect Express (PCIe) controller, a Universal Serial Bus(USB) controller and/or a Serial Advanced Technology Attachment (SATA)controller.

According to Example 10 there is provided at least one computer-readablestorage medium having instructions stored thereon which when executed bya processor result in the following operations for configuration ofInput/Output (I/O) controller lane access of a system. The operationsmay include: detecting a change request, the change request to modifythe configuration from an existing configuration to a new configuration;verifying that the new configuration is valid based on a stock keepingunit (SKU) associated with the system; and if the verification issuccessful, storing the new configuration in non-volatile memory andresetting the system.

Example 11 may include the subject matter of Example 10, and theconfiguration includes an I/O controller to lane mapping, a laneenablement selection or a lane width.

Example 12 may include the subject matter of Examples 10 and 11, furtherincluding providing the new configuration to the I/O controllers fromthe non-volatile memory, after resetting the system.

Example 13 may include the subject matter of Examples 10-12, and theverifying further includes verifying an I/O controller to lane mapping,verifying a lane enablement selection and verifying a lane width.

Example 14 may include the subject matter of Examples 10-13, furtherincluding, if the verification fails, signaling an error.

Example 15 may include the subject matter of Examples 10-14, and thechange request detection is performed during a power state transition ofthe system from a lower power state to a higher power state.

Example 16 may include the subject matter of Examples 10-15, and thechange request detection is performed by a Basic Input Output System(BIOS).

Example 17 may include the subject matter of Examples 10-16, furtherincluding receiving the change request from an agent external to thesystem.

According to Example 18 there is provided a method for configuration ofInput/Output (I/O) controller lane access of a system. The method mayinclude: detecting a change request, the change request to modify theconfiguration from an existing configuration to a new configuration;verifying that the new configuration is valid based on a stock keepingunit (SKU) associated with the system; and if the verification issuccessful, storing the new configuration in non-volatile memory andresetting the system.

Example 19 may include the subject matter of Example 18, and theconfiguration includes an I/O controller to lane mapping, a laneenablement selection or a lane width.

Example 20 may include the subject matter of Examples 18 and 19, furtherincluding providing the new configuration to the I/O controllers fromthe non-volatile memory, after resetting the system.

Example 21 may include the subject matter of Examples 18-20, and theverifying further includes verifying an I/O controller to lane mapping,verifying a lane enablement selection and verifying a lane width.

Example 22 may include the subject matter of Examples 18-21, furtherincluding, if the verification fails, signaling an error.

Example 23 may include the subject matter of Examples 18-22, and thechange request detection is performed during a power state transition ofthe system from a lower power state to a higher power state.

Example 24 may include the subject matter of Examples 18-23, and thechange request detection is performed by a Basic Input Output System(BIOS).

Example 25 may include the subject matter of Examples 18-24, furtherincluding receiving the change request from an agent external to thesystem.

Example 26 may include the subject matter of Examples 18-25, furtherincluding generating the change request on a processor of the system.

According to Example 27 there is provided a system for configuration ofInput/Output (I/O) controller lane access of a system. The system mayinclude: means for detecting a change request, the change request tomodify the configuration from an existing configuration to a newconfiguration; means for verifying that the new configuration is validbased on a stock keeping unit (SKU) associated with the system; and ifthe verification is successful, means for storing the new configurationin non-volatile memory and resetting the system.

Example 28 may include the subject matter of Example 27, and theconfiguration includes an I/O controller to lane mapping, a laneenablement selection ora lane width.

Example 29 may include the subject matter of Examples 27 and 28, furtherincluding means for providing the new configuration to the I/Ocontrollers from the non-volatile memory, after resetting the system.

Example 30 may include the subject matter of Examples 27-29, and theverifying further includes means for verifying an I/O controller to lanemapping, verifying a lane enablement selection and verifying a lanewidth.

Example 31 may include the subject matter of Examples 27-30, furtherincluding, if the verification fails, means for signaling an error.

Example 32 may include the subject matter of Examples 27-31, and thechange request detection is performed during a power state transition ofthe system from a lower power state to a higher power state.

Example 33 may include the subject matter of Examples 27-32, and thechange request detection is performed by a Basic Input Output System(BIOS).

Example 34 may include the subject matter of Examples 27-33, furtherincluding means for receiving the change request from an agent externalto the system.

Example 35 may include the subject matter of Examples 27-34, furtherincluding means for generating the change request on a processor of thesystem.

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention,in the use of such terms and expressions, of excluding any equivalentsof the features shown and described (or portions thereof), and it isrecognized that various modifications are possible within the scope ofthe claims. Accordingly, the claims are intended to cover all suchequivalents. Various features, aspects, and embodiments have beendescribed herein. The features, aspects, and embodiments are susceptibleto combination with one another as well as to variation andmodification, as will be understood by those having skill in the art.The present disclosure should, therefore, be considered to encompasssuch combinations, variations, and modifications.

1-26. (canceled)
 27. A System-on-a-Chip (SoC) comprising: a plurality ofInput/Output (I/O) controllers; a plurality of lanes; a lane mappingmodule to multiplex at least one of said I/O controllers to at least oneof said lanes based on a configuration; a first processor to detect achange request, said change request to modify said configuration from anexisting configuration to a new configuration; and a second processorto: verify that said new configuration is valid based on a stock keepingunit (SKU) associated with said SoC; and, if said verification issuccessful, store said new configuration in non-volatile memory andreset said SoC.
 28. The system of claim 27, wherein said configurationcomprises an I/O controller to lane mapping, a lane enablement selectionor a lane width.
 29. The system of claim 27, wherein said I/Ocontrollers load said new configuration from said non-volatile memory,after said reset.
 30. The system of claim 27, wherein said verificationof said new configuration further comprises verifying an I/O controllerto lane mapping, verifying a lane enablement selection and verifying alane width.
 31. The system of claim 27, wherein said change requestdetection is performed during a power state transition of said SoC froma lower power state to a higher power state.
 32. The system of claim 27,wherein said change request is received from an agent external to saidSoC.
 33. The system of claim 27, wherein said first processor is toexecute a Basic Input Output System (BIOS).
 34. The system of claim 27,wherein said second processor is a management engine microcontroller.35. The system of claim 27, wherein said plurality of Input/Output (I/O)controllers comprise a Peripheral Component Interconnect Express (PCIe)controller, a Universal Serial Bus (USB) controller and/or a SerialAdvanced Technology Attachment (SATA) controller.
 36. At least onecomputer-readable storage medium having instructions stored thereonwhich when executed by a processor result in the following operationsfor configuration of Input/Output (I/O) controller lane access of asystem, said operations comprising: detecting a change request, saidchange request to modify said configuration from an existingconfiguration to a new configuration; verifying that said newconfiguration is valid based on a stock keeping unit (SKU) associatedwith said system; and if said verification is successful, storing saidnew configuration in non-volatile memory and resetting said system. 37.The computer-readable storage medium of claim 36, wherein saidconfiguration comprises an I/O controller to lane mapping, a laneenablement selection or a lane width.
 38. The computer-readable storagemedium of claim 36, further comprising providing said new configurationto said I/O controllers from said non-volatile memory, after resettingsaid system.
 39. The computer-readable storage medium of claim 36,wherein said verifying further comprises verifying an I/O controller tolane mapping, verifying a lane enablement selection and verifying a lanewidth.
 40. The computer-readable storage medium of claim 39, furthercomprising, if said verification fails, signaling an error.
 41. Thecomputer-readable storage medium of claim 36, wherein said changerequest detection is performed during a power state transition of saidsystem from a lower power state to a higher power state.
 42. Thecomputer-readable storage medium of claim 36, wherein said changerequest detection is performed by a Basic Input Output System (BIOS).43. The computer-readable storage medium of claim 36, further comprisingreceiving said change request from an agent external to said system. 44.A method for configuration of Input/Output (I/O) controller lane accessof a system, said method comprising: detecting a change request, saidchange request to modify said configuration from an existingconfiguration to a new configuration; verifying that said newconfiguration is valid based on a stock keeping unit (SKU) associatedwith said system; and if said verification is successful, storing saidnew configuration in non-volatile memory and resetting said system. 45.The method of claim 44, wherein said configuration comprises an I/Ocontroller to lane mapping, a lane enablement selection or a lane width.46. The method of claim 44, further comprising providing said newconfiguration to said I/O controllers from said non-volatile memory,after resetting said system.
 47. The method of claim 44, wherein saidverifying further comprises verifying an I/O controller to lane mapping,verifying a lane enablement selection and verifying a lane width. 48.The method of claim 47, further comprising, if said verification fails,signaling an error.
 49. The method of claim 44, wherein said changerequest detection is performed during a power state transition of saidsystem from a lower power state to a higher power state.
 50. The methodof claim 44, wherein said change request detection is performed by aBasic Input Output System (BIOS).
 51. The method of claim 44, furthercomprising receiving said change request from an agent external to saidsystem.
 52. The method of claim 44, further comprising generating saidchange request on a processor of said system.